1. Field of the Invention
The present invention relates to a main memory controller used in controlling a main memory connected to an engineering workstation or the like having a single CPU or multi-CPU configuration,
2. Description of the Related Arts
An engineering workstation or the like generally has a cache memory between a main memory and a CPU thereof to increase memory access speed. When such a cache memory keeps data which have been rewritten (owned status), the data must be output from the cache memory after the output of data from the main memory is invalidated to allow readout from the bus master of another CPU, an I/O controller, or the like.
Such a conventional main memory controller can not output data until the latest timing at which a signal for invalidating data in the main memory may be output from the cache memory in response to an access to the CPU. Thus, the speed of the access from the CPU to the main memory is delayed by the time required for determining the presence of data in the cache regardless of whether the cache memory stores data or not, which results in the problem that there is reduction in the efficiency of data transfer corresponding to such a delay.